1. Field of the Invention
The present invention relates to a pulse filter, and more particularly to a pulse filter in a half-bridge or full-bridge driver.
2. Description of the Related Art
To describe the related art of the present invention, the relation between a pulse filter and a half-bridge or full-bridge driver shall be introduced first. Please refer to FIG. 1, which shows the architecture of a typical half-bridge driver 100. As shown in FIG. 1, the typical half-bridge driver 100 at least includes a pulse generator 101, a level shifter 102, a pulse filter 103, and a latch 104.
The pulse generator 101 is used for generating a first clock signal CLK and a second clock signal CLKB, wherein the first clock signal CLK is interleaved with the second clock signal CLKB. The level shifter 102 is used to up shift the first clock signal CLK and the second clock signal CLKB from low side to provide counterpart signals for the pulse filter 103 at high side. The pulse filter 103 is used for cancelling a common-mode glitch interference accompanying the power lines of VBOOT and HB, and generating a set signal vSET and a reset signal vRESET to the latch 104. The latch 104 is used for sending a signal to a driver to switch a high-side power MOSFET. During the switching, a glitch is generated due to the capacitive characteristic of a capacitor CBOOT, i.e., the voltage difference hold between the two plates of a capacitor will not change abruptly. As a result, a certain period the capacitor takes to reach a stable state causes a glitch period. The pulse filter 103 is therefore used to deal with the glitch problem to prevent false triggering of the latch 104.
Please refer to FIG. 2, which shows a circuit diagram of a prior art pulse filter 200 driving a latch 210. As shown in FIG. 2, the prior art pulse filter 200 includes PMOS transistors 201-204, and resistors 205-208.
When VS is at a low level and VR is at a high level, the PMOS transistors 201 and 203 will be turned off and the PMOS transistors 202 and 204 will be turned on, and the set signal VSET will be at a low level, and the reset signal VRESET will be at a high level. When VS is at a high level and VR is at a low level, the PMOS transistors 201 and 203 will be turned on and the PMOS transistors 202 and 204 will be turned off, and the set signal VSET will be at a high level, and the reset signal VRESET will be at a low level.
When a glitch couples on both the set signal VSET and the reset signal VRESET, both the PMOS transistors 203 and 204 will remain in their previous conduction states—(on, off) or (off, on)—because their source-gate voltages will remain unchanged (if both VS and VR experience same voltage deviation).
However, as the resistors 205-206 and the resistors 207-208 can be mismatched due to manufacture process variations, VS and VR can experience different voltage deviations to cause false triggering of the latch 210. Besides, the PMOS transistors 201 and 202 can be broken down when a large common-mode glitch takes place on the power line VBOOT but the voltage deviations at the gates of the PMOS transistors 201 and 202 are relatively small due to low impedance values seen into the sources of the PMOS transistors 203 and 204.
Therefore, there is a demand to provide a robust pulse filter for a bridge driver.